1. Field of the Invention
The present invention relates generally to digital signal processing, and more particularly to processing of digital signals using a circuit suitable for adiabatic charging.
2. State of the Art
The operation of electronic devices such as amplifiers and digital logic gates using charge-controlling devices such as MOSFETs is well understood to dissipate power according to the charging and discharging of capacitance within the circuits. In conventional VLSI CMOS circuitry, a capacitive load comprised of gate capacitance and metal wiring capacitance is charged to a power supply voltage, V, and is discharged to 0 volts, thus dissipating energy=CV.sup.2 as heat. In this cycle of charging and discharging a load capacitance, the only way to reduce the energy dissipation in a conventional CMOS circuit is to reduce the supply voltage, V. This increases the sensitivity of the circuit to background noise and thus increases the probability of malfunction. The well-known principal of adiabatic charging allows charge to be controlled without the controlling or controlled charge giving up their energy as heat. The adiabatic charging principal asserts that it is possible to cycle a signal from 0 to V volts through a resistance without dissipating CV.sup.2 of energy, by slowing down the speed of energy transport between the power supply and the circuit's signal node. The energy advantage can be readily understood by assuming a constant current source that delivers the charge CV over a time period T. The dissipation through the channel resistance R is then: EQU E=P.times.T=I.sup.2 .times.R.times.T=(CV/T).sup.2 .times.R.times.T
This reduces to: EQU E=(RC/T).times.CV.sup.2
This equation shows that it is possible to reduce the dissipation to an arbitrary degree by increasing the switching time to ever-larger values. By doing so, energy that would otherwise be dissipated in the resistance is conserved for later use, thus dramatically reducing the power required to accomplish a given logical operation. This is commonly accomplished by using a capacitor-inductor tank circuit to supply power to an adiabatic circuit, and by using inverse logic functions to alternately charge and discharge the circuit's capacitive load through the inductor-capacitor tank supply. The time, T, required to charge or discharge the capacitive load is kept long by the inductor, which acts as a constant-current source to supply charge to the load capacitance.
The advantages of adiabatic charging promised in theory have been difficult to realize in practice. Logical functions useful for digital or analog electronic systems require the cascading or pipelining of many adiabatic circuit stages to form an electronic system.
One approach to cascading or pipelining a plurality of adiabatic logic functions was discussed in an article entitled, "Low-Power Digital Systems Based on Adiabatic-Switching Principles," Athas et al, IEEE Trans. on VLSI Systems, p. 398 (Mar. 1994). This document describes an implementation of adiabatic reversible-pipeline logical functions using only reversible functions. This requirement for reversible logic adds a formidable constraint to the logic designer designing an electronic system with this method. The Athas et al document gives an example of a three-bit adder circuit which, because of the reversibility requirement, requires 20 times the number of devices and 32 times the area of a conventional adder using the same technology and laid out by the same designer. The power dissipation of the extra circuit elements required to meet the reversibility requirement can actually cause the reversible-pipeline adiabatic circuit to dissipate more power than a conventional CMOS circuit.
The pipelining technique of the Athas et al document poses significant drawbacks to the circuit designer, namely, the daunting task of designing an electronic system that consists of completely reversible logic, and also the severe penalty in the amount of circuitry and chip area required.
Another approach has been to eliminate the need for reversible pipelining by using diodes to control the direction of current flow. In U.S. Pat. No. 5,422,582, "Diode Coupled CMOS Logic Design For Quasi-Static Resistive Dissipation With Multi-output Capability", Avery et al describe a technique for pipelining adiabatic circuits where complimentary CMOS logic is used to alternately charge and discharge a capacitive load adiabatically. In the Avery et al patent, n-channel CMOS logic functions are used to discharge capacitive loads while their respective inverse p-channel CMOS logic functions are used to recharge capacitive loads with diodes controlling the flow of current for discharging and recharging. The use of diodes imposes a power penalty because the voltage drop across the diode is a constant fixed by the physical properties of the diodes: no matter how small the charging current is the power used in the diodes will always be governed by the relation P=I.times.V.sub.t, where V.sub.t is the diode threshold voltage. The use of dual complimentary circuitry to evaluate a single logical function also imposes a penalty of added VLSI chip area and effectively doubles the amount of power needed to generate the intended logical function.
Another approach to pipelined adiabatic circuits was proposed in the document, "Adiabatic Computing with the 2N-2N2D Logic Family", by Kramer et al (1994 Symposium on VLSI Circuits Digest of Technical Papers). The Kramer et al document proposes a precharged adiabatic circuit which relies on diodes to control the direction of current flow and uses inverse logic functions to create complimentary signal pairs. The Kramer et al pipelining scheme does not permit the output of one stage to simultaneously drive the input of another stage being evaluated during the same evaluation phase. This is a significant limitation to the designer of a pipelined adiabatic electronic system. The use of dual complimentary circuitry to evaluate a single logical function also imposes a significant penalty on VLSI chip area and doubles the power required to generate the desired function.
Accordingly, it would be highly desirable to provide an implementation of adiabatic pipelined logic which is not restricted to the use of reversible logic functions, which does not impose the power penalty of using diodes to control current flow, which does not impose the chip area penalty of dual complimentary circuitry for each function to be evaluated, yet which can allow the simultaneous evaluation of several cascaded logic functions, and which can realize the significant power savings promised by the theory of adiabatic charging.